The present invention relates to a method and circuit for correcting error in a cache memory, and more particularly to error correction of a control field of a store-in cache memory in a multi-processor system.
In a conventional multi-processor system in which each processor has a store-in cache memory, each cache memory has one of four cache statuses (e.g., "IV", "CE", "CS" and "DE") to maintain a cache coherency.
A cache status "IV" represents that a data in a corresponding line is invalid. A cache status "CE" represents that a data in a corresponding line is coherent with a data stored in a main storage (e.g., "clean"), and that no other cache memory has a copy of the data (e.g., "exclusive"). A cache status "CS" represents that a data in a corresponding line is coherent with a data stored in a main storage (e.g., "clean"), and that any other cache memories (e.g., at least one cache memory) may have a copy of the data (e.g., "shared"). A cache status "DE" represents that a data in a corresponding line is not coherent with a data stored in a main storage (e.g., "dirty"), and that no other cache memory has a copy of the data (e.g., "exclusive").
In the conventional system, when the cache status is "DE", if it is erroneously determined to be "CS" or "CE" because of a fault in the control field, a data representing sole or exclusive information in the system is lost. Thus, because the fault in the store-in cache causes a fault in the main storage, reliability of the control field should be enhanced.
Referring to FIG. 1, a conventional cache memory has a three-bit control field comprising a valid bit (V), a shared bit (S), and a dirty bit (D). The valid bit represents that a data in a corresponding line is valid if the valid bit is active (e.g., V="1"). The shared bit represents that a data in a corresponding line is shared by any other cache memories (e.g., at least one cache memory) if the shared bit is active (e.g., S="1") . The dirty bit represents that a data in a corresponding line is not coherent with a data stored in a main storage (e.g., D="1").
The conventional cache memory has cache status "IV" when all bits in the control field are inactivated (e.g., V="0", S="0", and D="0"). The conventional cache memory has cache status "CS" when only the dirty bit is inactivated (e.g., V="1", S="1", and D="0"). The conventional cache memory has cache status "DE" when only the shared bit is inactivated (e.g., V="1", S="0", and D="1"). The conventional cache memory has cache status "CE" when only the valid bit is activated (e.g., V="1", S="0", and D="0").
Referring to FIG. 2, in the conventional cache memory, it is determined whether an error has occurred in the control field in step S901. If any error is detected, then the error is reported to a processor or a diagnostic processor in step S908, and a process is aborted (e.g., the system is shutdown). If no error is detected, then a cache status is determined depending on the control field according to steps S902 through S907.
However, this conventional cache memory has a problem in that the control field cannot be corrected while error in the control field is detected. For example, when error in the valid bit is detected, the valid bit cannot be corrected based on the shared bit or the dirty bit.
Furthermore, in the conventional cache memory, since error in the control field causes a system shutdown, the system's reliability is decreased.